CAN 发送数据不成功，TX高电平

这是从dsPIC33-PIC24-FRM,-CAN-Flexible-Data-Rate-(FD)-Protocol-Module-DS70005340B.pdf文件中下载的CANFD发送数据例程
烧录程序后，dsp TX引脚一直为高电平，请问是什么原因，是没有数据么？
（设置CAN时钟40M, 波特率：数据段2M,中裁段1M） 芯片DSPIC33CK256MP506

/* This code example demonstrates a method to configure the CAN FD module to transmit Standard and
Extended ID CAN FD messages. This uses CAN1, TXQ and FIFO1. TXQ size is 1 and FIFO1 size is 2. */
// DSPIC33CK256MP508 Configuration Bit Settings
// 'C' source line config statements
// FSEC
#pragma config BWRP = OFF               // Boot Segment Write-Protect bit (Boot Segment may be written)
#pragma config BSS = DISABLED           // Boot Segment Code-Protect Level bits (No Protection (other than BWRP))
#pragma config BSEN = OFF               // Boot Segment Control bit (No Boot Segment)
#pragma config GWRP = OFF               // General Segment Write-Protect bit (General Segment may be written)
#pragma config GSS = DISABLED           // General Segment Code-Protect Level bits (No Protection (other than GWRP))
#pragma config CWRP = OFF               // Configuration Segment Write-Protect bit (Configuration Segment may be written)
#pragma config CSS = DISABLED           // Configuration Segment Code-Protect Level bits (No Protection (other than CWRP))
#pragma config AIVTDIS = OFF            // Alternate Interrupt Vector Table bit (Disabled AIVT)
// FBSLIM
#pragma config BSLIM = 0x1FFF           // Boot Segment Flash Page Address Limit bits (Boot Segment Flash page address  limit)
// FSIGN
// FOSCSEL
#pragma config FNOSC = PRI              // Oscillator Source Selection (Primary Oscillator (XT, HS, EC))
#pragma config IESO = ON                // Two-speed Oscillator Start-up Enable bit (Start up device with FRC, then switch to user-selected oscillator source)
// FOSC
#pragma config POSCMD = XT              // Primary Oscillator Mode Select bits (XT Crystal Oscillator Mode)
#pragma config OSCIOFNC = OFF           // OSC2 Pin Function bit (OSC2 is clock output)
#pragma config FCKSM = CSECME           // Clock Switching Mode bits (Both Clock switching and Fail-safe Clock Monitor are enabled)
#pragma config PLLKEN = ON              // PLL Lock Status Control (PLL lock signal will be used to disable PLL clock output if lock is lost)
#pragma config XTCFG = G3               // XT Config (24-32 MHz crystals)
#pragma config XTBST = ENABLE           // XT Boost (Boost the kick-start)
// FWDT
#pragma config RWDTPS = PS1048576       // Run Mode Watchdog Timer Post Scaler select bits (1:1048576)
#pragma config RCLKSEL = LPRC           // Watchdog Timer Clock Select bits (Always use LPRC)
#pragma config WINDIS = ON              // Watchdog Timer Window Enable bit (Watchdog Timer operates in Non-Window mode)
#pragma config WDTWIN = WIN25           // Watchdog Timer Window Select bits (WDT Window is 25% of WDT period)
#pragma config SWDTPS = PS1048576       // Sleep Mode Watchdog Timer Post Scaler select bits (1:1048576)
#pragma config FWDTEN = ON              // Watchdog Timer Enable bit (WDT enabled in hardware)
// FPOR
#pragma config BISTDIS = DISABLED       // Memory BIST Feature Disable (mBIST on reset feature disabled)
// FICD
#pragma config ICS = PGD3              // ICD Communication Channel Select bits (Communicate on PGEC1 and PGED1)
#pragma config JTAGEN = OFF             // JTAG Enable bit (JTAG is disabled)
#pragma config NOBTSWP = DISABLED       // BOOTSWP instruction disable bit (BOOTSWP instruction is disabled)
// FDMTIVTL
#pragma config DMTIVTL = 0xFFFF         // Dead Man Timer Interval low word (Lower 16 bits of 32 bitDMT window interval (0-0xFFFF))
// FDMTIVTH
#pragma config DMTIVTH = 0xFFFF         // Dead Man Timer Interval high word (Uper 16 bits of 32 bitDMT window interval (0-0xFFFF))
// FDMTCNTL
#pragma config DMTCNTL = 0xFFFF         // Lower 16 bits of 32 bit DMT instruction count time-out value (0-0xFFFF) (Lower 16 bits of 32 bit DMT instruction count time-out value (0-0xFFFF))
// FDMTCNTH
#pragma config DMTCNTH = 0xFFFF         // Upper 16 bits of 32 bit DMT instruction count time-out value (0-0xFFFF) (Upper 16 bits of 32 bit DMT instruction count time-out value (0-0xFFFF))
// FDMT
#pragma config DMTDIS = OFF             // Dead Man Timer Disable bit (Dead Man Timer is Disabled and can be enabled by software)
// FDEVOPT
#pragma config ALTI2C1 = OFF            // Alternate I2C1 Pin bit (I2C1 mapped to SDA1/SCL1 pins)
#pragma config ALTI2C2 = OFF            // Alternate I2C2 Pin bit (I2C2 mapped to SDA2/SCL2 pins)
#pragma config ALTI2C3 = OFF            // Alternate I2C3 Pin bit (I2C3 mapped to SDA3/SCL3 pins)
#pragma config SMBEN = SMBUS            // SM Bus Enable (SMBus input threshold is enabled)
#pragma config SPI2PIN = PPS            // SPI2 Pin Select bit (SPI2 uses I/O remap (PPS) pins)
// FALTREG
#pragma config CTXT1 = OFF              // Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits (Not Assigned)
#pragma config CTXT2 = OFF              // Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 2 bits (Not Assigned)
#pragma config CTXT3 = OFF              // Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 3 bits (Not Assigned)
#pragma config CTXT4 = OFF              // Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 4 bits (Not Assigned)
// FBTSEQ
#pragma config BSEQ = 0xFFF             // Relative value defining which partition will be active after device Reset; the partition containing a lower boot number will be active (Boot Sequence Number bits)
#pragma config IBSEQ = 0xFFF            // The one's complement of BSEQ; must be calculated by the user and written during device programming. (Inverse Boot Sequence Number bits)
// #pragma config statements should precede project file includes.
// Use project enums instead of #define for ON and OFF.

#include <xc.h>
//void  RX(void);
#define MAX_WORDS 100
unsigned int __attribute__((aligned(4)))CanTxBuffer[MAX_WORDS];
#define MAX_RX_WORDS 100
unsigned int __attribute__((aligned(4)))CanRxBuffer[MAX_RX_WORDS];
/*data structure to implement a CANFD  message buffer. */
/* CANFD Message Time Stamp */
typedef unsigned long CANFD_MSG_TIMESTAMP;
/* CAN TX Message Object Control*/
typedef struct _CANFD_TX_MSGOBJ_CTRL {
    unsigned DLC:4;
    unsigned IDE:1;
    unsigned RTR:1;
    unsigned BRS:1;
    unsigned FDF:1;
    unsigned ESI:1;
    unsigned SEQ:7;
    unsigned unimplemented1:16;
} CANFD_TX_MSGOBJ_CTRL;
/* CANFD TX Message ID*/
typedef struct _CANFD_MSGOBJ_ID {
    unsigned SID:11;
    unsigned long EID:18;
    unsigned SID11:1;
    unsigned unimplemented1:2;
} CANFD_MSGOBJ_ID;
/* CAN TX Message Object*/
typedef union _CANFD_TX_MSGOBJ {
    struct  {
        CANFD_MSGOBJ_ID id;
        CANFD_TX_MSGOBJ_CTRL ctrl;
        CANFD_MSG_TIMESTAMP timeStamp;
    } bF;
    unsigned int word[4];
    unsigned char byte[8];
} CANFD_TX_MSGOBJ;

typedef struct _CANFD_RX_MSGOBJ_CTRL {
    unsigned DLC:4;
    unsigned IDE:1;
    unsigned RTR:1;
    unsigned BRS:1;
    unsigned FDF:1;
    unsigned ESI:1;
    unsigned unimplemented1:2;
    unsigned FilterHit:5;
    unsigned unimplemented2:16;
} CANFD_RX_MSGOBJ_CTRL;
/* CANFD RX Message ID*/

/* CANFD RX Message Object */
typedef union _CANFD_RX_MSGOBJ {
    struct  {
        CANFD_MSGOBJ_ID id;
        CANFD_RX_MSGOBJ_CTRL ctrl;
        CANFD_MSG_TIMESTAMP timeStamp;
    } bF;
    unsigned int word[4];
    unsigned char byte[8];
} CANFD_RX_MSGOBJ;


int main(void)
{   
    unsigned int index;
    ANSELC = 0x0000;
   
  /* Place code to set device speed here. For this example the device speed should be set at
40 MHz (i.e., the device is operating at 40 MIPS). */  
    CLKDIVbits.PLLPRE = 2;
    PLLDIVbits.POST1DIV = 2;
    PLLDIVbits.POST2DIV = 1;
    PLLFBD = 80 ;   //40 MIPS Fcy, 80 FOSC
      
    __builtin_write_OSCCONH(0x03);          /* New Oscillator PRI w/ PLL */
    __builtin_write_OSCCONL(0x01);         /* Enable Switch */
   /* Wait for Switch to happen */
    while(OSCCON & 0x0001);
    Nop();
    Nop();
    Nop();
    while(!OSCCONbits.LOCK);        
   /* Set up the CAN clock generater for 40 MIPS and enable the CAN clock generator. */
//ConfigureCanfdClockFor40MIPS();
    CANCLKCONbits.CANCLKSEL = 2; //can clock source FPLLO
    CANCLKCONbits.CANCLKDIV = 3;  // div by 4
    CANCLKCONbits.CANCLKEN = 1;
   
    /* The dsPIC33CH device features I/O remap. This I/O remap configuration for the CAN FD
module can be performed here.
   * Board used : explorer 16/32 board
   * Slot : Slot B */   
   _CAN1RXR = 47;     //C1RX to RC9 (pin 37)   
   _RP46R= 0x15;      //C1TX to RD9 (pin 38)
  
    /* Enable the CANFD module */
    C1CONLbits.CON = 1;
    /* Place CAN module in configuration mode */
    C1CONHbits.REQOP = 4;
    while(C1CONHbits.OPMOD != 4);
    /* Initialize the C1FIFOBA with the start address of the CAN FIFO message buffer area. */
    C1FIFOBAL = (unsigned int) &CanTxBuffer;
    /* Set up the CANFD module for 1Mbps of Nominal bit rate speed and 2Mbps of Data bit rate. */
    C1NBTCFGH = 0x001E;
    C1NBTCFGL = 0x0707;
    C1DBTCFGH = 0x000E;
    C1DBTCFGL = 0x0303;
    C1TDCH = 0x0002; //TDCMOD is Auto
    C1TDCL = 0x0F00;
    /* Configure CANFD module to enable Transmit Queue and BRS*/  
    C1CONLbits.BRSDIS = 0x0;
    C1CONHbits.STEF = 0x0; //Don't save transmitted messages in TEF
    C1CONHbits.TXQEN = 0x1;
    /* Configure TXQ to transmit 1 message*/
    C1TXQCONHbits.FSIZE = 0x0; // single message
    C1TXQCONHbits.PLSIZE = 0x7; // 64 bytes of data
    /* Configure FIFO1 to transmit 2 messages*/
    C1FIFOCON1Hbits.FSIZE = 0x1; //2 messages
    C1FIFOCON1Hbits.PLSIZE = 0x2; //16 bytes of data
    C1FIFOCON1Lbits.TXEN = 0x1; // Set TXEN bit ,transmit fifo
    /* Place the CAN module in Normal mode. */
    C1CONHbits.REQOP = 0;
    while(C1CONHbits.OPMOD != 0);
   
   /* Get the address of the message buffer to write to. Load the buffer and */
    /* then set the UINC bit. Set the TXREQ bit next to send the message. */
    CANFD_TX_MSGOBJ *txObj;
    /* Transmit message from TXQ - CANFD base frame with BRS*/
    /* SID = 0x100 , 64 bytes of data */
    txObj = (CANFD_TX_MSGOBJ *)C1TXQUAL;   
    txObj->bF.id.SID = 0x100;
    txObj->bF.id.EID = 0x0000;
    txObj->bF.ctrl.BRS = 1 ;  //Switch bit rate
    txObj->bF.ctrl.DLC = 0xF; //64 bytes
    txObj->bF.ctrl.FDF = 1; // CANFD frame
    txObj->bF.ctrl.IDE = 0; //Standard frame
    for (index=0;index<0x40;index++ )
    {
       txObj->byte[index+8] = 0x5A ; // 64 bytes of 0x5A
    }
    C1TXQCONLbits.UINC = 1; // Set UINC bit
    C1TXQCONLbits.TXREQ = 1; // Set TXREQ bit
    /* Transmit message 0 from FIFO 1 - CANFD base frame with BRS*/
    /* SID = 0x300 , 16 bytes of data */
    txObj = (CANFD_TX_MSGOBJ *)C1FIFOUA1L;   
    txObj->bF.id.SID = 0x300;
    txObj->bF.id.EID = 0x0000;
    txObj->bF.ctrl.BRS = 1 ;  //Switch bit rate
    txObj->bF.ctrl.DLC = 0xA; //16 bytes
    txObj->bF.ctrl.FDF = 1; // CANFD frame
    txObj->bF.ctrl.IDE = 0; //Standard frame
    for (index=0;index<0x10;index++ )
    {
       txObj->byte[index+8] = 0xA5 ; // 16 bytes of 0xA5
    }
    C1FIFOCON1Lbits.UINC = 1; // Set UINC bit
    C1FIFOCON1Lbits.TXREQ = 1; // Set TXREQ bit
    /* Transmit message 1 from FIFO 1 - CANFD base frame with BRS*/
    /* SID = 0x500, EID = 0xC000, 12 bytes of data */
    txObj = (CANFD_TX_MSGOBJ *)C1FIFOUA1L;   
    txObj->bF.id.SID = 0x500;
    txObj->bF.id.EID = 0xC000;
    txObj->bF.ctrl.BRS = 1 ;  //Switch bit rate
    txObj->bF.ctrl.DLC = 0x9; //12 bytes
    txObj->bF.ctrl.FDF = 1; // CANFD frame
    txObj->bF.ctrl.IDE = 1; //Standard frame
    for (index=0;index<0xC;index++ )
    {
       txObj->byte[index+8] = 0x55 ; // 12 bytes of 0x55
    }
    C1FIFOCON1Lbits.UINC = 1; // Set UINC bit
    C1FIFOCON1Lbits.TXREQ = 1; // Set TXREQ bit   
   
  
}