移相DC-DC的移相问题

希望各位大牛看到能够给我解答一下。研一开题想做双向全桥DC-DC，在做单移相的时候DSP输出的驱动信号正常，虽然期间也有一些硬件问题，但好歹解决了一些，但现在我遇到了问题，改了几天都不行。
在双移相或者三移相的时候，DSP输出的驱动始终对不上，要么就是只移一个，始终无法输出三个相对移相的驱动。下面是程序，也已修改过时基里的参数，就是不行。下面附上驱动程序。
void InitEPwm1Example()
{
   // Setup TBCLK
   EPwm1Regs.TBPRD = 3000;           // Set timer period
   EPwm1Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero
   EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Symmetrical mode
   EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Master module
   EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
   EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Sync down-stream module
   EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
   EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
   EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
   EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero
   EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // set actions for EPWM1A
   EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;
   EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
   EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;      // Active Hi complementary
   EPwm1Regs.DBFED = 300;
   EPwm1Regs.DBRED = 300;
   // Interrupt where we will change the Compare Values
   EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;     // Select INT on Zero event
   EPwm1Regs.ETSEL.bit.INTEN = 1;                // Enable INT
   EPwm1Regs.ETPS.bit.INTPRD = ET_1ST;           // Generate INT on 1st event
}
void InitEPwm2Example()
{
   EPwm2Regs.TBPRD = 3000;           // Set timer period
   EPwm2Regs.TBPHS.half.TBPHS = 800; // Phase = 300/900 * 360 = 120 deg
   EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Symmetrical mode
   EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Slave module
   EPwm2Regs.TBCTL.bit.PHSDIR = TB_UP; // Count DOWN on sync (=120 deg)
   EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
   EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through
   EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
   EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
   EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
   EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero
   EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // set actions for EPWM2A
   EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR;
   EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
   EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi Complementary
   EPwm2Regs.DBFED = 300;
   EPwm2Regs.DBRED = 300;
   // Interrupt where we will change the Compare Values
   EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;        // Select INT on Zero event
   EPwm2Regs.ETSEL.bit.INTEN = 1;                   // Enable INT
   EPwm2Regs.ETPS.bit.INTPRD = ET_1ST;              // Generate INT on 1st event
}
void InitEPwm3Example(void)
{
   // Setup TBCLK
   EPwm3Regs.TBPRD = 3000;           // Set timer period
   EPwm3Regs.TBPHS.half.TBPHS = 300; // Phase = 300/900 * 360 = 120 deg
   EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Symmetrical mode
   EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Slave module
   EPwm2Regs.TBCTL.bit.PHSDIR = TB_UP; // Count UP on sync (=240 deg)
   EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;
   EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through
   EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
   EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
   EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
   EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero
   EPwm3Regs.AQCTLA.bit.CAU = AQ_SET; // set actions for EPWM3Ai
   EPwm3Regs.AQCTLA.bit.CAD = AQ_CLEAR;
   EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
   EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
   EPwm3Regs.DBFED = 300;
   EPwm3Regs.DBRED = 300;
   // Interrupt where we will change the Compare Values
   EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;     // Select INT on Zero event
   EPwm3Regs.ETSEL.bit.INTEN = 1;                // Enable INT
   EPwm3Regs.ETPS.bit.INTPRD = ET_1ST;           // Generate INT on 1st event
}