Verilog里写了一个计时器,导入simplis仿真报错:<<<<<<<< Error Message ID: 5061 >>>>>>>>Verilog Pre-Processor process returned an undefined or error code.
<<<<<<<< Error Message ID: 5064 >>>>>>>>
Unrecoverable error occurred in the SIMPLIS Verilog Interface.
vss_root.v文件如下:
module vss_root() ;
reg S2V_N51 ; // SIMPLIS to Verilog
wire V2S_N50 ; // Verilog to SIMPLIS
reg S2V_N49 ; // SIMPLIS deck path: X$U57.1
reg S2V_N48 ; // SIMPLIS deck path: X$U56.2
reg S2V_N47 ; // SIMPLIS deck path: X$U56.1
wire V2V_P91 ; // SIMPLIS deck path: 331
reg S2V_P176 ; // SIMPLIS deck path: 436
wire V2S_P180 ; // SIMPLIS deck path: 430
wire V2S_P181 ; // SIMPLIS deck path: 431
wire V2S_P182 ; // SIMPLIS deck path: 432
wire V2S_P183 ; // SIMPLIS deck path: 433
wire V2S_P184 ; // SIMPLIS deck path: 434
wire V2S_P189 ; // SIMPLIS deck path: 429
assign V2S_N50 = S2V_N51 ;
// SIMPLIS deck path: X$U56.!V_VERILOG
wire U0_OP0 ; // Port flag
wire U0_IP0 ; // Port clk_240m
wire U0_IP1 ; // Port rst
wire U0_IP2 ; // Port Vtr
assign V2V_P91 = U0_OP0 ;
assign U0_IP0 = S2V_N47 ;
assign U0_IP1 = S2V_N48 ;
assign U0_IP2 = S2V_P176 ;
counter_time U0( .flag(U0_OP0), .clk_240m(U0_IP0), .rst(U0_IP1), .Vtr(U0_IP2) ) ;
求助是什么问题导致的。
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