BOOST PFC VS BUCK PFC: 来源于TI资料

受yuguang: https://bbs.21dianyuan.com/105789.html 影响,再加之TI的活动如火如荼...
在一文章上看到了BUCK PFC与BOOST PFC的一些优缺点,如下,供大家参考:


A. Boost PFC Performance Advantages and Challenges
••Achieves very low THD, offering probably the best possible PF. 可以实现极低THD,以达最优PF值.
••High output voltage—volumetrically-efficient energy-storage capacitors, good hold-up.高压输出(较高单位体积能量存储能力),有良好的输出维持能力.
••Low-side boost switch allows easy gate drive and switch current sense. 低压BOOST开关驱动简易且容易实现开关电流检测. (这个大家有共识)
••Direct forward path from AC input to bulk storage capacitor eases lightning surge management. AC侧直接进入BULK储能电容,可以减缓雷击浪涌的不利影响.
••Wealth of available control ICs and design/analysis literature to aid designers. 已有大量的IC及分析文献可以帮助设计者完成设计.

同理,有利也有弊端:
••Output voltage must always be higher than the instantaneous AC input voltage—for universal or high-line AC input (up to 264 VAC), bus voltage must be set at about 400 VDC.输出电压必须一直高于输入电压,不管是全电压还是高电压时,输出BUS总线电压必须设定在400V左右.
••Requires a subsequent high-voltage primary regulation/isolation stage to step down to practical voltage levels required by most electronic loads.对于大多数电子负载而言,400V高压不可以直接用,必须再加一级隔离降压或是调节电路.
••High bus voltage causes higher level of common mode (CM) EMC noise. 高压母线电压产生较高的共模噪声.
••No inrush limitation at start-up (this is the flip side of the surge advantage listed earlier), so a potentially dissipative or costly inrush limiting mechanism is required. 由于没有开机启动冲击电流限制(这与前面提到的抗雷击浪涌的优点恰好相反), 所以需要一种: 要么用便宜消耗型冲击电流抑制电路或是要么选择高成本的抑制机制.
••Considerable drop in efficiency at low line because of the high voltage differential between the AC input voltage and the bus voltage and the consequent effect on PFC choke design.由于输出电压与输入电压的压差,这样导到在低压输入时效率会下降,同时会影响到PFC电感的设计.



B. Buck PFC Performance Advantages and Challenges
••The high-voltage AC input is immediately bucked to a lower voltage level by the PFC front-end which results in: 由于高压输入直接进入低压侧这样:
• Easier functional safety spacing in the subsequent regulation/isolation stage. 后级的调整电路相对来说更安全.
• Lower downstream voltages, improving robustness and reliability.后级电压低,鲁棒性及可靠性提高了.
• Low bus voltage results in lower CM noise. 低压母线电压产生较压的共模噪声.
• Lower bus voltage for downstream stage,allowing more efficient designs, using lower voltage MOSFETs with better figures of merit. 允许使用参数更好的低压MOSFET,效率可以得到提高.
••Lower input-to-output voltage differential across PFC choke benefits includeFC电感上由于是较低的输入-输出电压差:
• The ability to use a lower inductance value when compared to a boost PFC. 相对于BOOST PFC来说,可以使用更小的电感.
• Input-output differential voltage across the choke varies in the opposite direction compared to a boost—thus a lower voltage differential at low line where efficiency is most challenged.
• The buck has to work hardest at high line voltages where currents are much lower,whereas the boost works hardest at low line voltages when it boosts the most and currents are simultaneously the highest. BUCK在最高电压输入(此时为最恶劣工况)的时候电流更小, 而BOOST在最低电压的时候(此时为最恶劣工况)输入电流也高.
••Easy to control. Control flexibility helps achieve good THD and PF without the need for an AC line-sense reference and multiplier.控制更加灵活,可以实现低THD及PF要求,不需要AC线电压检测参考及乘法器.
••Inherent “free” inrush limitation at start-up; no dedicated inrush limiting mechanism is required. 天然的无冲击电流(开机时),不需要冲击电流限制机置.

粗一看,BUCK PFC更具优势...但缺点我们能否接受:


••Inherent AC line current “cross-over” distortion limits achievable THD and PF performance.由于固有的线电流存在畸变,限制了THD及PF的性能水平.
••Requires use of either a high-side drive for the buck PFC switch or a high-side bus-voltage sense,depending on configuration used. 依不同的配置,需要采用高压侧驱动或是高压侧母线电感检测. (这可能是一大硬伤)
••No direct path from AC input to bulk-storage capacitor, complicating surge management.BUCK阻断了电网电压流入BULK电容, 故增加了抗浪涌难度.
••Lower output voltage results in less efficient bulk-capacitor energy storage, so bulk capacitors need to be larger and/or hold-up time is lower. 由于母线输出电压低,BULK电容储能少,所以BULK电容需要更大,因而保持时间相应减少.
••A higher percentage bus-voltage ripple compared to boost PFCs requires voltage loops with lower bandwidths and a slower transient response.相比于BOOST PFC电路,BUCK 母线电压存在大量的纹波分量,这样电压环需要更窄的带宽及更慢的动态响应.
••Limitation of available control IC, expertise and design/analysis literature to aid designers. 控制IC及相关设计参考资料少.

以上是个人看到的一些,译的一些,其他大家补充...